UA-RCL University of Arizona Reconfigurable Computing Lab

CEDR: A Holistic Software and Hardware Design Environment for FPGA-Integrated Heterogeneous Systems

As the FPGAs are being embedded in all layers of computing infrastructure from edge to HPC scales, system designers continue to explore design methodologies that leverage increased levels of heterogeneity to meet target performance goals or constraints. In line with this, we have developed CEDR, an open-source, unified compilation and runtime framework designed for FPGA-integrated heterogeneous systems. CEDR allows applications, scheduling heuristics, and accelerators to be co-designed in a cohesive manner. This tutorial builds on the educational class conducted on the CEDR framework during ESWEEK’23 with a focus on FPGA-integrated heterogeneous systems. It caters to audiences with diverse backgrounds and varying levels of expertise, providing an opportunity for exploration and study of FPGA-based computing in heterogeneous contexts.

We will start with an overview of CEDR, and then we will explore how CEDR (i) allows naive application developers to utilize FPGA-based acceleration within heterogeneous environments, (ii) enables system designers to sweep hardware compositions and measure their impact on realistic workload scenarios, and (iii) provides a rich environment for resource management developers to design new scheduling policies. Throughout the tutorial, our common goal is lifting the barriers to research and enabling productive application deployment on FPGA-integrated heterogeneous systems.


Archival materials:

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