RANC is a highly flexible environment that enables rapid experimentation with neuromorphic architectures in both software via C++ simulation and hardware via FPGA emulation. RANC enables hardware architects and application engineers to investigate and tune parameters of their neuromorphic architecture that would otherwise be unavailable on a purely prefabricated ASIC. This level of flexibility creates an environment that allows for optimizing architectures based on application insights as well as prototyping future neuromorphic architectures that can support new classes of applications entirely.
Our article GPU-RANC: A CUDA Accelerated Simulation Framework for Neuromorphic Architectures was accepted for publication in the 2024 Neuro-Inspired Computational Elements (NICE) workshop
Our article A Novel Implementation Methodology for Error Correction Codes on a Neuromorphic Architecture was accepted for publication in the IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems
Our article RANC: Reconfigurable Architecture for Neuromorphic Computing was accepted for publication in the IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems
Our paper FPGA Based Emulation Environment for Neuromorphic Architectures was accepted to the 2020 IPDPS Reconfigurable Architectures Workshop
Currently, we have implemented an FPGA emulation environment that is behaviorally compatible with IBM's TrueNorth architecture. We are strengthening our core capabilities by building a library of applications on top of our emulation environment to further stress its capabilities and explore architectural optimizations.
In the future, among other architectural explorations, we will expand to support Intel's Loihi and related architectures to better assess the impacts and benefits of features such as on chip learning or multicast routing.