LDPC Simulation Testbed

About

This project presents an FPGA based high throughput and modular simulation testbed for rapid simulation of decoders for Low Density Parity Check (LDPC) codes. The users can replace different modules of this testbed to incorporate their own hard-decision decoders for rapid characterization.

LDPC codes are a popular choice for employment in several cutting edge communication standards such as 5G, WiFi, WiMax, 10 Gigabit Ethernet etc.. With the increasing popularity of LDPC codes, the research to obtain decoders with better error correction performance and reduced hardware footprint is becoming prominent as well. Analyzing and improving the decoders require detailed large scale simulations. General purpose CPU based software execution of such simulators have become infeasible due to long simulation time. Furthermore, developing such simulators on hardware platform (e.g. FPGA) requires significant amount of effort which is outside the scope of research on decoders.

The testbed reduces the duration of large scale simulations down to order of hours from order of years on a single core CPU. Furthermore, this highly flexible testbed reduces design time significantly by enabling users to easily integrate their desired decoders with this platform.

Publications and News

1. B. Unal, M. S. Hassan, J. Mack, N. Kumbhare and A. Akoglu, "Design of High Throughput FPGA-Based Testbed for Accelerating Error Characterization of LDPC Codes," 2019 International Conference on ReConFigurable Computing and FPGAs (ReConFig), Cancun, Mexico, 2019, pp. 1-8, doi: 10.1109/ReConFig48160.2019.8994785.
2. B. Unal, A. Akoglu, F. Ghaffari and B. Vasic, "Hardware Implementation and Performance Analysis of Resource Efficient Probabilistic Hard Decision LDPC Decoders," IEEE Transactions on Circuits and Systems I: Regular Papers, vol. 65, no. 9, pp. 3074-3084, Sept. 2018.
3. B. Unal, F. Ghaffari, A. Akoglu, D. Declercq, B. Vasic, Analysis and Implementation of Resource Efficient Probabilistic Gallager B LDPC Decoder, The 15th IEEE International New Circuits and Systems Conference (NEWCAS 2017), Strasbourg, France, pp. 333-336, June 25-28, 2017.

Project Status and Future Work

Currently, our testbed supports several hard-decision decoding algorithms such as Gallager B (GaB), Probabilistic GaB (PGaB), Gradient Descent Bit Flipping (GDBF), and Probabilistic GDBF (PGDBF). The FPGA based testbed allows users to specify different simulation parameters before launching the execution, and returns the statistics to the user for calculating the error correction performance of decoder under test.

In future works, we aim to add more recent hard-decision decoding algorithms like Probabilistic Parallel Bit Flipping (PPBF), Tabu-list Random-penalty GDBF (TRGDBF) etc. to the decoder library. We further aim to take the testbed on MPSoC. Taking advantage of this platform, the aim is to make the testbed more flexible and capable. Besides statistics, it should be able to provide detailed information to the users to identify the weaknesses of the simulated decoders.